The present invention relates to field programmable gate array (FPGA) technology. More particularly, the present invention relates to programmable elements for use in FPGA devices, and specifically to programmable elements configured from resistive random access memories (ReRAMs) formed from individual ReRAM devices.
FPGA integrated circuits are versatile, but are large therefore are cost sensitive and consume considerable amounts of power. Making them area efficient has been a major goal.
ReRAMs have been proposed for fabricating multiplexers in FPGA devices. A ReRAM device is a two-terminal device including an ion source layer and a solid electrolyte layer. To program a ReRAM device a voltage potential placed across the two terminals of the device causes metal ions from the ion source layer to migrate into the solid electrolyte layer to form a conductive path across the entire device. The ReRAM device is erased by applying a voltage potential across the two terminals of the device opposite in polarity to the potential that was used to program the device. This causes the metal ions to migrate back into the ion source layer from the solid electrolyte layer to eliminate the conductive path across the entire device. Most proposals suggest using a pair of ReRAM devices in back-to-back orientation (in which either the ion source layers or the solid electrolyte layers of the two ReRAM devices are connected together) so that one device is always in the reverse bias condition to avoid disturb (unintentional programming of the ReRAM memory device to its on state) during logic switching.
FIG. 1A is a schematic diagram of a prior-art ReRAM memory cell 10 formed from a pair of ReRAM devices 12 and 14 arranged in a back-to-back configuration. The terminal of each of ReRAM devices 12 and 14 having the angled end is the ion-source terminal of the device. A programming transistor 16 has its drain coupled to the common node 18 of the ion-source ends of the ReRAM devices 12 and 14. The source of programming transistor 16 is coupled to a Y-decode line 20 and its gate is coupled to an X-decode line 22.
During normal circuit operation, a first end 24 of the memory cell 10 is connected to a first circuit node of the circuit in which the memory cell 10 is used and a second end 26 of the memory cell 10 is connected to a second circuit node of the circuit in which the memory cell 10 is used. When the ReRAM devices 12 and 14 are erased, the first node 24 remains unconnected to the second node 26 and when the ReRAM devices 12 and 14 are programmed, the first node 24 is connected to the second node 26 through the memory cell 10. As will be appreciated by persons of ordinary skill in the art, the first node 24 and the second node 26 may be any nodes in the integrated circuit that the ReRAM cell 10 will programmably connect to one another. Non-limiting examples include inputs and outputs of clocked or static logic function circuits, or interconnect conductors in a circuit routing architecture of an integrated circuit that has user-programmable connections.
To program memory cell 10, the ReRAM devices are individually programmed. A first programming potential is placed on Y-decode line 20, a second programming potential is placed on first and second ends 24 and 26 of the ReRAM cell 10, and programming transistor 16 is turned on by applying an appropriate voltage to its gate from X-decode line 20. To erase memory cell 10, the ReRAM devices are individually erased. A first erase potential is placed on Y-decode line 20, a second erase potential is placed on first and second ends 24 and 26 of the ReRAM cell 10, and programming transistor 16 is turned on by applying an appropriate voltage to its gate from X-decode line 20. ReRAM cells 12 and 14 can be programmed and erased either simultaneously, as described above, or individually by controlling the voltage potentials delivered to first and second ends 24 and 26 of ReRAM cell 10 and to X-decode line 22 and Y-decode line 20. The design of circuits for supplying such program and erase voltages at appropriate voltage levels, polarities, and timings for resistive random access memory devices formed using particular materials and having specific geometries are well within the level of ordinary skill in the art.
FIG. 1B is a cross-sectional diagram of an illustrative embodiment of an implementation of the memory cell 10 of FIG. 1A. The semiconductor substrate, or well, 30 includes diffused regions 32 and 34 that serve as the drain and source, respectively, of transistor 16 of FIG. 1. The source 34 is connected to the Y-decode line 20 of FIG. 1. Polysilicon line 36 forms the gate of transistor 16 of FIG. 1A and can also serve as the X-decode line 22 (shown in FIG. 1) for programming the memory cell 10.
A contact 38 connects the drain region 32 of the transistor 16 to a segment 40 of a first metal interconnect line over which the ReRAM devices 12 and 14 of FIG. 1A will be formed. A contact 42 connects the segment 40 of the first metal interconnect line to the solid electrolyte layer 44 of ReRAM device 12 (shown in dashed lines in FIG. 1B). The ion source 46 of the first ReRAM device 12 is connected by contact 48 to segment 50 of a second metal interconnect line. Similarly, a contact 52 connects the segment 40 of the first metal interconnect line to the solid electrolyte layer 54 of ReRAM device 14 (shown in dashed lines in FIG. 1B). The ion source 56 of the first ReRAM device 14 is connected by contact 58 to segment 60 of the second metal interconnect line. Persons of ordinary skill in the art will appreciate that the designations of first and second metal interconnect lines are used for convenience.
Referring now to FIG. 2, a typical top view of a prior-art pair of 4:1 multiplexers 70 using prior-art ReRAM cells as described above is shown. Segments 72, 74, 76, and 78 of a second metal interconnect line form Input 1, Input 2, Input 3, and Input 4 of the multiplexers. Segments 80 and 82 of the second metal interconnect line form Output 1 and Output 2 of the multiplexers. Segments 84, 86, 88, and 90 of a first metal interconnect line form the first metal line segment 40 for each of the ReRAM cells depicted in FIG. 1B used to connect Input 1, Input 2, Input 3, and Input 4 of the multiplexers to Output 1 of the first multiplexer and segments 92, 94, 96, and 98 of the first metal interconnect line form the first metal line segment 40 for each of the ReRAM cells depicted in FIG. 1B used to connect Input 1, Input 2, Input 3, and Input 4 of the multiplexers to Output 2 of the second multiplexer.
The small squares in dashed lines represent the ReRAM devices 12 and 14 for each ReRAM cell used in the multiplexers 70 of FIG. 2. To connect an input to an output, both ReRAM devices 12 and 14 in the selected multiplexer input/output pair must be programmed to make connections. For the first multiplexer, ReRAM devices 12-1-1 and 14-1-1 are programmed to connect Input 1 to Output 1; ReRAM devices 12-1-2 and 14-1-2 are programmed to connect Input 2 to Output 1; ReRAM devices 12-1-3 and 14-1-3 are programmed to connect Input 3 to Output 1; and ReRAM devices 12-1-4 and 14-1-4 are programmed to connect Input 4 to Output 1. For the second multiplexer, ReRAM devices 12-2-1 and 14-2-1 are programmed to connect Input 1 to Output 2; ReRAM devices 12-2-2 and 14-2-2 are programmed to connect Input 2 to Output 2; ReRAM devices 12-2-3 and 14-2-3 are programmed to connect Input 3 to Output 2; and ReRAM devices 12-2-4 and 14-2-4 are programmed to connect Input 4 to Output 2. Bitlines 22a and 22b are used to turn on the programming transistors (not shown) to program the ReRAM cells for the first and second multiplexers, respectively.
A major issue that arises when using ReRAM memory cells formed from pairs of ReRAM devices in back-to-back orientation is the possible failure of a memory cell due to one of the ReRAM devices either becoming short circuited or losing its ability to be switched off once it is programmed. With one of the devices stuck in the on state, the probability that disturb is likely to eventually cause an erased ReRAM memory cell, in which both ReRAM devices are supposed to be switched to their erased state, to fail by disturbing the working erased ReRAM device to its programmed state during normal use of the FPGA device creates a significant endurance issue for integrated circuits incorporating these memory cells, particularly in circuits such as, but not limited to, multiplexers and look-up tables (LUTs) where unpredictable logic level voltages will appear at one end of ReRAM cells disposed in unselected circuit paths.
In the exemplary prior-art multiplexer circuit shown in FIG. 2, assume Input 1 is programmably connected to Output 1 by programming the ReRAM memory cell formed by ReRAM devices 14-1-1 and 12-1-1, and further that Input 1 carries a ground potential associated with a logic 0 state. If it is further assumed that Input 2 is connected to a circuit node the carries a VDD potential representing a logic 1 state, a potential device disturb problem will arise if either ReRAM device 14-1-2 or 12-1-2 shorts or fails to erase because then the entire logic potential of VDD will exist across the erased one of ReRAM devices 14-1-2 or 12-1-2.